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ARBS

Simulate. Stimulate. Validate.Accelerate ECU Testing.

ARBS is a modernised, open framework engineered to dramatically lower test execution overhead and enable the shift in ECU testing for Software Defined Vehicles.

Open & Extensible

Built on Python with open specifications.

Real-Time Performance

Low-latency Socket/CAN transit latency.

Zero-License Hardware

Optimised for enterprise budgets.

Reliable & Scalable

Secure, scalable and ready for high-node labs.

How ARBS works

High-performance simulation and stimulation over standard interfaces.

User / Test System

Interactive dashboard for telemetry, control and analysis.

User Visualisation Console

ARBS Hardware

Processes unit running optimised C-bindings and Python runtimes.

4-Core ARM | Ubuntu RT-OS

Device Under Test

Automotive ECU listening to cyclic simulation bus loads.

DUT Input Interface Rx

Powerful Capabilities

Native Python Environment

  • Leverage the power of Python for rapid automation.
  • Build custom test scripts and workflows.

Zero-License Hardware

  • Runs on cost-effective hardware.
  • Optimised for enterprise deployments.

Real-Time Performance

  • <1.2 ms SocketCAN transit latency.
  • Deterministic and reliable execution.

Open Specifications

  • Standard real-time Linux baseline.
  • Interoperable and future-proof architecture.

DevOps & CI/CD Ready

  • Continuous integration with automation pipelines.
  • Script-driven configuration and execution.

Advanced Signal Control

  • Native DBC parsing and multi-signal generation.
  • Dynamic fault injection and condition simulation.

Platform Strengths

  • Python-first environment
  • Standard Linux baseline
  • Low execution latency
  • High-node lab scalability
  • Secure SocketCAN interfaces
ARBS platform architecture illustration

Key Features

  • Native DBC Parsing
  • Multi-Signal Generator
  • Dynamic Fault Injection
  • High-throughput Logging (BLF/MDF4/ASC/CSV)
  • Automated XML Reporting

Roadmap Alignment – Ready for Tomorrow

Lab ECU Simulation

ARBS mimics absent hardware modules (restbus simulation).

EOL Factory Verification

Hardware form factor scales onto physical test rigs.

SDV Readiness

Next-generation architecture for Software Defined Vehicles.

Intuitive Dashboard.Complete Control.

Monitor signals, control simulations, inject faults and capture logs – all from a unified dashboard.

  • Real-time signal monitoring
  • Scenario control & playback
  • Fault injection & error simulation
  • Logging & analysis export
ARBS Console dashboard